In order to digitally process a video signal (hereinafter referred to as video format signal) obtained by reading and demodulating a signal from a recording medium such as a video disk or a video tape, it is necessary to have a high frequency clock pulse which is synchronized with the video format signal. For this reason, a clock pulse generating circuit is constructed to phase lock a phase locked loop (PLL) circuit with the horizontal synchronizing signal in the format signal for clock pulse generation. In a clock pulse generating circuit as mentioned above, handling disturbance generated by the vertical equalizing pulse in the composite synchronizing signal becomes a concern.
In an effort to prohibit disturbances due to the vertical equalizing pulse, various circuit constructions have been tried in the past. For example, in one circuit the vertical equalizing pulse is deleted from the composite synchronizing signal through analog processing, leaving only the horizontal synchronizing signal, then, the resultant signal is input into the PLL circuit. Japanese Patent Unexamined Publication No. Sho. 63-234673 discloses to keep the PLL circuit in an open state during the vertical flyback period to stop the operation of the phase comparator within the PLL circuit.
However, in the former case where the deletion of the vertical equalizing pulse is performed by analog processing, the number of components becomes large and adjustment of the time constant becomes necessary. Also, stopping the operation of the phase comparator in the PLL circuit results in a deviation of the generated clock pulses over that period.